BS EN 61691-2-2001 pdf download.Behavioural languages Part 2 : VHDL multilogic system for model interoperability.
This BS EN 61691-2 is embodied in the Std_logic_ 1164 package package body along with this clause I documentation. The information annc AA is a guide to users and is not part of this standard, but suggests ways in which one might use
1.2 Conforniance with this standard
The following conformance rules shall apply as they
a) No modifications shall be made to the package declaration
hI The Std_logicj 164 package body represents the formal Std_logic_ 1164 package declaration. Implementers of this package body as it is; or they may choose to implement to the user. Users shall not implement a semantic that
2. Std_logic_1 164 package declaration
— Title : Std_logic_I 164 multialuc logic system
— Library : This package shall he compiled into a library symbolically named IEEE.
Developers: IEEE model standards group (par I 164)
Purpose This packages defines a standard for designers
to use in describing the
used in VHDL modcling.
The value systcm in Stdjogic_l 164 was developed to modcl the logic system is named “std_ulogic” where the comprising the type have a specified semantic and a intemperate, one must interpret the meaning of each of
Type std_ulogic is
‘U’. Uninitialized state
X. Forcing Unknown etc. ‘0’, Forcing Zero ‘I’. ForcingOne
High Impedance
Weak Unknown
Weak Zero
‘I-I’. Weak One
Don’t (‘are modeling
A.2 handling strengths
Behavioral modeling techniques rarely require knowledge “strength stripper” functions have been designed “forcing” strength counterparts.
Once in forcing strength. the model can simply respond to stripping is done by using one of the following functions:
To_X0l (…) converts ‘1’ and ‘H’ to ‘0’ and
To_UXO I C,..) converts ‘L’ and ‘H’ to ‘0’ and to ‘X.
A.3 Use of the uninitialized value
The U’ value is located in the first position of automatically initialized to ‘U’ unless expressly
Uninitialized values were designed to provide a means of uninitialized state since the time of system XNOR. and NOT have been designed to propagate ‘U’
The propagation of ‘U’s through a circuit gives properly initialized. The AND gate example that follows
A.4 Behavioral modeling for ‘U’ propagation
For behavioral modeling where ‘U’ propagation is system, as far as the modeler is conccrncd, thereby
A. ‘U’s related to conditional expressions
Case statements, “if’ expressions, and selected path for ‘U’ state propagation in order to
A.6 Structural modeling with logical tables
The logical tables are designed to generate output values of the nine-slate system passes through any of the arises lix a weak or floating strength to be propagated model developer shall be certain to assign the
A.7 X-handling: assignment of X’s
In assignments. the X and ‘-‘ values means that synthesis tools arc allowed to generate either ‘X’ usually appears during transitions or as a conditions, such as in the following waveform assignment:
S < X after I ns, ‘I’ after 5 ns
where the current value of S becomes indeterminate after
AJ Modeling with don’t care’s
A.X.l Use of the don’t care stale In snlhesis niodels
For synthesis, a VII DL program is a specification of the order to simulate) real circuits, The former deals with function of a circuit from an electrical point of view, assumption that the VHDL models will be logical function of the logic type to logical function. The motivation for do not specify the behavior of the circuit to be built, such simulation artifacts to remain in models for these references, the user is assuming only the kind of occur in hardware.
AJI.2 Semantics of ‘-‘
In designing the resolution function and the various syntactic shorthand fbr ‘X’, provided fbr becomes X’ as soon as it is operated upon and value represents either a I’ or a as
A.9 Resolution function
In digital logic design, there are a number of occasions together. The most common of which is tri.state1’ buses in which memory data ports arc connected to each to controlling microprocessors. Another common case is loaded signal path. In each of these cases, the VHI)L devices be ‘resolved’ signal types.
Focusing on resolution: when two signals’ values are that wire. For example. if two parallel buftixs both is in the high- impedance state 2 and another signal values will result in a value of • I’
The resolution function built into Std_logic_ 1164 impedance values and forcing values dominate over weak values.
A.1O Using Std_ulogic vs. SW_logic
In deciding whether to use the resolved signal or.BS EN 61691-2-2001 pdf download.