ANSI VITA-31.1-2003 pdf download American National Standard for Gigabit Ethernet on VME64x Backplanes
2 P0 Connector Pin Assignment
2.1 Introduction The IEC 61076-4-101 2 mm connector that is used for the VME64x P0 has 7 rows of pins. The outside two rows, z and f, are shield pins and the c row is an additional ground pin. These pins are committed to logic ground at the backplane and plug-in board. The center five rows of the connector are available for I/O. Each VME64x board (node board) can have one or two Ethernet connections on the P0 connector. The Ethernet connection uses two slices for a single 10/100/1000 Mb/s Ethernet port, as shown in Figure 2-1. This port also supports Auto-Negotiation as defined in ANSI/IEEE 802.3. A 10BASE-T or 100BASE-T connection will use the Tx and Rx pairs for communication. A 1000BASE-T connection will use all four pairs for communication.
2.2 Ethernet Port Pin Assignment The IEEE 802.3u 10/100 Mb/s full-duplex Ethernet connections use two pairs of pins labeled Tx and Rx in Figure 2-1. IEEE 802.3ab 1000Mb/s connections use four pairs of pins labeled as BI_DA, BI_DB, BI_DC, and BI_DC in Figure 2-1. This pin assignment corresponds to the MDI signals in IEEE 802.3.
Figure 2-2 shows where the Ethernet ports are located on the P0 connector. Port A uses positions 2 and 3. Port B uses positions 4 and 5.
Note: The pins in connector position 1 and position 6 cannot be used for I/O because of the possibility of interfering with the Ethernet signals.
3 Fabric Slot Pin Assignment 3.1 Introduction The Ethernet ports on each VME64x Node Board are connected to one or two router or switch boards that are installed in the fabric slots in the backplane. For redundancy or improved performance, two router or switch boards can be used. The fabric slot pin assignment in this standard is identical to the pin assignment defined in the PICMG 2.16 Packet Switched Backplane specification. The router or switch boards for PICMG 2.16 systems can be used in VITA 31.1 systems. Note: The Fabric Slot uses the CompactPCI style of numbering the pins from bottom to top.