EN 60191-6-17-2011 pdf download.Mechanical standardization of semiconductor devices -Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages -Design guide for stacked packages -Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and PPFLGA).
This part of IEC 60191 provides outline drawings and dimensions for stacked packages and individual stackable packages In the form of FBGA or FLGA.
2 Normative references
The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document applies.
IEC 6019 1-6, Mechanical standardization of semiconductor devices — Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device package
IEC 60191-6-5, Mechanical standardization of semiconductor devices — Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages – Design guide for fine-pitch ball grid array (FBGA)
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60191-6 and the following apply.
3.1
individual stackable package
package with an array of metallic balls or lands on the underside of the package for the purpose of surface-mount on a printed circuit board and an array of footprints (lands) on the upper side of the package for stacking packages
NOTE The indavidual stackable cavity-up FLGA package Is a part of this specificaUon on the premise of stacking a cavity-down FBGA with cavity-up FLGA.
3.2
stacked package
assembly of multiple individual stackable packages in a stacked configuration
NOTE The top package can be a standard FBGA specified in EC 60191-6-5 without any footprints on the upper side of the package. The stand-off height of this standard package, however, shall follow this design guide
3-3
mould cap height (A2)
height of the mould cap which contains wire-bonded die or of the exposed flip chip-bonded die with respect to the upper substrate surface of the package
3.4
distance between the mould cap edge and innermost balls (F)
distance between the mould cap edge of the lower package and the innermost terminals of the upper package of the stacked package
3.5
upper side land grid pitch (e1)
grid pitch of the footprints (lands) on the upper side of the individual stackable package. They will be interconnected with the terminals of a mating upper package
3.6
parallelism tolerance of the mould cap surface (y.,)
parallelism tolerance of the top mould-cap surface of the stacked package or the individual stackable package with respect to the seating plane (datum J), which is established by contact of the crowns of the balls
NOTE For the stacked package, y” is defined as the parallelism tolerance of the top-component surface wtth regard to the seating plane of the lowest component.
3.7
coplanarity (y)
flatness tolerance controlling the lowest points of the terminals of the individual stackable package or the stacked package
3.8
diameter of the upper side lands (b2)
diameter of the upper side lands, which will be bonded to the terminals of the mating upper package
4 Terminal position numbering
When a package is viewed from the terminal side with the index corner in the bottom left corner position, terminal rows are lettered from bottom to top starting with A, then B, C,.., AA, AB, etc., while terminal columns are numbered from left to right starting with 1. Terminal positions are designated by a row-column grid system and shown as alphanumeric identification, e.g.. Al, 81 • or AC34.
The letters I. 0, 0, S, X and Z are not used for naming the terminal rows.EN 60191-6-17-2011 pdf download.