ANSI NCITS TR-25-1999 pdf download Information Technology一 Fibre Channel – Methodologies for Jitter Specificaton
In addition clause 7.3.2 of FC-PH-3 includes a normative receive eye diagram (figure 31) for copper inter- connect and the associated table (table 12) which implies a total jtter at point R of 0,56 UI for inter-closure and 0,58 UI for intra-closure. It also has a statement in note 1 that the receiver must accommodate more jiter than listed in table 12 for allowance of external EMI induced events. These additional jtter require- ments can be better specified and implemented using the concepts in this technical report.
7.2 Fibre channel storage implementation Actual Fibre Channel system implementations do not easily ft into the compliance interfaces specified in FC-PHn. These interface locations and the jtter budgets at points other than S need to be unambiguously defined. This is particularly true given the inclusion of various active elements used in Fibre Channel imple- mentations.
A Fibre Channel Port consists of the functional blocks shown in figure 4. From a timing and jtter perspec- tive, the following characteristics must be noted. Fibre Channel uses pleisochronous timing where a port transmits data at a slightly different frequency from its receive data frequency. Elastic storage exists within the protocol function to absorb the frequency differences as well as the maximum wander present in the link. The serializer function is responsible for suppressing jtter components present in the port from propa- gating onto the link. The deserializer must recover a bit clock from the serial data which reliably allows the deserializer to provide parallel data and a recovered byte clock to the protocol function.
A Fibre Channel link is a duplex serial data connection between two ports including the serializer, deserial- izer, PMD, connectors, and cable assemblies. A link is necessary for communication between two ports. A link includes a minimum of a pair of transmitter-receiver connections. A TxRx connection is a simplex link consisting of one transmitter-receiver pair. A link and a TxRx connection is shown in figure 5.
A port by definition contains protocol itelligence, elasticity buffers to absorb wander, and locally timed serial data transmission. Other components in a TXRX connection may be used which attenuate jtter or reamplifty the signal to improve the signal quality. In actual system implementations, these can include active buffers, port bypass circuits, or retimers. An example of a complex system implementation for stor- age application using Fibre Channel Arbitrated Loop is as shown in figure 6. In this system, a link between the host adapter Port and the disk drive in Port 2 is rather complex. This link would include a HA TX to HDD RX connection through a hub with repeaters, an enclosure with repeaters, and a backpanel with one PBC and a HDD TX to HA RX connection through multiple HDD Ports acting as retimer circuits, several port bypass circuits, an enclosure repeater, and a hub repeater.